VLSI Design Flow / ASIC Desgn Flow

 VLSI Design Flow

In VLSI (very-large-scale-integration) circuits designing process is highly complex. It is divided into several blocks of designing. The flow of the chip design is shown below. This flow is also called as ASIC (application specific integrated circuit) flow. Earlier steps are high-level; later design steps are at lower level abstraction. At the end of the process, before element's geometric shape and electrical properties.

The steps of the VLSI design flow are discussed in detail below. For further reading on physical design algorithms.

System Specification.  

Chip architects, circuit designers, product marketers, operation managers, and layout and library designers collectively define the overall goals and high-level requirements of the system. These goals and requirements span functionality, performance, physical dimensions and production technology.

Architectural Design.

A basic architecture must be determined to meet the system specifications. Example decisions are

•  Integration of analog and mixed-signal blocks
•  Memory management – serial or parallel – and the addressing scheme
•  Number and types of computational cores, such as processors and digital signal processing (DSP) units – and particular DSP algorithms
•  Internal and external communication, support for standard protocols, etc.
• Usage of hard and soft intellectual-property (IP) blocks
•  Pinout, packaging, and the die-package interface
•  Power requirements
• Choice of process technology and layer stacks

Functional and logic design. 

Once the architecture is set, the functionality and connectivity of each module (such as a processor core) must be defined. During functional design, only the high-level behavior must be determined. That is, each module has a set of inputs, outputs, and timing behavior.

Logic design is performed at the register-transfer level (RTL) using a hardware description language (HDL) by means of programs that define the functional and timing behavior of a chip. Two common HDLs are Verilog and VHDL. HDL mod ules must be thoroughly simulated and verified. Logic synthesis tools automate the process of converting HDL into low-level circuit elements. That is, given a Verilog or VHDL description and a technology library, a logic synthesis tool can map the described functionality to a list of signal nets, or netlist, and specific circuit elements such as standard cells and transistors.

Circuit design. 

For the bulk of digital logic on the chip, the logic synthesis tool automatically converts Boolean expressions into what is referred to as a gate-level netlist, at the granularity of standard cells or higher. However, a number of critical, low-level elements must be designed at the transistor level; this is referred to as circuit design.

Physical design.

During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers. 

Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. The several steps in physical design are

1. Partitioning
2. Floorplanning
3. Power and ground routing
4. Placement
5. Clock Tree Synthesis
6. Global routing
7. Detailed Routing
8. Timing closure

Physical verification. 

After physical design is completed, the layout must be fully verified to ensure correct electrical and logical functionality. Some problems found during physical verification can be tolerated if their impact on chip yield is negligible. In other cases, the layout must be changed, but these changes must be minimal and should not introduce new problems. Therefore, at this stage, layout changes are usually performed manually by experienced design engineers.

1. Design rule checking (DRC)
2. Layout vs Schematic (LVS)
3. Parasitic extraction
4. Antenna rule checking
5. Electrical rule checking (ERC)

Fabrication. 

The final DRC-/LVS-/ERC-clean layout, usually represented in the GDSII Stream format, is sent for manufacturing at a dedicated silicon foundry (fab). The handoff of the design to the manufacturing process is called tapeout, even though data transmission from the design team to the silicon fab no longer relies on magnetic tape [1.6]. Generation of the data for manufacturing is sometimes referred to as streaming out, reflecting the use of GDSII Stream. At the fab, the design is patterned onto different layers using photolithographic processes. Photomasks are used so that only certain patterns of silicon, specified by the layout, are exposed to a laser light source. Producing an IC requires many masks; modifying the design requires changes to some or all of the masks.

Packaging and testing. 

After dicing, functional chips are typically packaged. Pack- aging is configured early in the design process, and reflects the application along with cost and form factor requirements. Package types include dual in-line packages (DIPs), pin grid arrays (PGAs), and ball grid arrays (BGAs). After a die is posi- tioned in the package cavity, its pins are connected to the package’s pins, e.g., with wire bonding or solder bumps (flip-chip). The package is then sealed.

Manufacturing, assembly and testing can be sequenced in different ways.