OVERVIEW OF PHYSICAL DESIGN

Physical Design.

 During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers. The result of physical design is a set of manufacturing specifications that must subsequently be verified. Physical design is performed with respect to design rules that represent the physical limitations of the fabrication medium. For instance, all wires must be a prescribed minimum distance apart and have prescribed minimum width. As such, the design layout must be recreated in (migrated to) each new manufacturing technology.

Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.

–    Performance: long routes have significantly longer signal delays.

–    Area: placing connected modules far apart results in larger and slower chips.

–    Reliability: large number of vias can significantly reduce the reliability of the  circuit.

–   Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.

–    Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens.

 Due to its high complexity, physical design is split into several key steps.

–       Partitioning : breaks up a circuit into smaller subcircuits or modules, which can each be designed or analyzed individually.

–      Floorplanning : determines the shapes and arrangement of subcircuits or modules, as well as the locations of external ports and IP or macro blocks.

–       Power and ground routing : often intrinsic to floorplanning, distributes power (VDD) and ground (GND) nets throughout the chip.

–       Placement : finds the spatial locations of all cells within each block.

–      Clock network synthesis : determines the buffering, gating (e.g., for power management) and routing of the clock signal to meet prescribed skew and delay requirements.

–   Global routing : allocates routing resources that are used for connections; example resources include routing tracks in channels and in switchboxes.

–    Detailed routing : assigns routes to specific metal layers and routing tracks within the global routing resources.

–   Timing closure : optimizes circuit performance by specialized placement and routing techniques.

After detailed routing, electrically-accurate layout optimization is performed at a small scale. Parasitic resistances (R), capacitances (C) and inductances (L) are extracted from the completed layout, and then passed to timing analysis tools to check the functional behavior of the chip. If the analyses reveal erroneous behavior or an insufficient design margin (guardband) against possible manufacturing and environmental variations, then incremental design optimizations are performed.